1. Field of the Invention
Embodiments in the present disclosure relates generally to the field of computer networking, and in particular to techniques for improving processing power of network switches, routers, bridges and/or other types of network switching devices.
2. Description of the Related Art
The rapid growth of internet demand continues to push today's communication and data networks to support faster data rates and enhanced quality of services. Today's communication and data networks, such Ethernet networks, commonly comprise network nodes, such as switches and routers that forward and transport data packets to different destinations within the networks. The processing power and throughput of the network nodes may depend at least in part on the processing power of its packet processing application-specification integrated circuit (ASIC). Specifically, the network nodes use the packet processing ASIC to build and maintain forwarding tables, (e.g., tables that map media access control (MAC) addresses to ports) to properly route and forward data packets. Although the demand to increase throughput continues to grow, designs for improving the network nodes and their packet processing ASIC components may be constrained by cost, power, and size requirements.
The processing power of a packet processing ASIC is generally determined by its clock speed. Generally, the faster the clock speed, the more processing power and throughput the packet processing ASIC may provide to a network node for processing and forwarding data packets. When a packet processing ASIC is used to process data packets, the clock speed may limit the number of packets the packet processing ASIC is able to process for given time duration (e.g., about a second). In particular, a networking protocol, such as Ethernet, may be configured to transfer a set number of data packets per second to a port based on the protocol rate. For the packet processing ASIC to meet the protocol rate, the maximum number of ports the packet processing ASIC can process may be determined by the ASIC's clock speed divided by the number of data packets per second at a port. For example, a 10 Gigabit per second Ethernet link can transfer up to about 15 million packets in one second for a port. If a packet processing ASIC is configured to operate at about 480 megahertz (MHz), and assuming data packet processing requires one ASIC clock cycle, then the packet processing ASIC can potentially process up to 480 million packets per second or up to 32 ports of traffic. If 480 MHz is the upper limit of the clock speed in a specific semiconductor technology, implementing a packet processing ASIC that includes more than 32 ports of 10 Gigabit per second Ethernet becomes difficult. Unfortunately, as protocol rates continue to increase to handle ever growing amounts of network traffic, network nodes and the packet processing ASIC components may need to increase their processing throughput to manage the ever increasing amount of data traffic transported over modern networks.